1. Field of the Invention
This invention relates to a semiconductor device including a resistance element as part of a semiconductor integrated circuit.
2. Description of the Related Art
Resistance elements are extensively used in semiconductor integrated circuits for voltage control purposes such as the division and reduction of power supply and signal voltages, and for various other purposes. Exemplary resistance elements are disclosed by Japanese Patent Application Publication No. H07(1995)-111311 (hereinafter “Iwai”).
The resistance elements disclosed by Iwai are illustrated in schematic cross section in FIG. 1. The resistance elements shown in FIG. 1 are formed as a plurality of p+ diffused resistance regions 103 in the surface layer of an n-type silicon substrate 101. The silicon substrate 101 is covered by a thin oxide film 121. The diffused resistance regions 103 are formed by implantation of impurity ions such as boron ions into the silicon substrate 101 through the thin oxide film 121. A low-resistance polycrystalline silicon (polysilicon) layer 107 covers all parts of the oxide film 121 in the resistance element area, except the parts directly over the diffusion regions 103. The polysilicon layer 107 is held at the power supply voltage to block the effects of electric fields created by higher layers of wiring (not shown) and prevent the formation of p-type inversion layers in the substrate areas directly below the polysilicon layer 107, so that no current can leak between adjacent diffused resistance regions 103.
Recently, however, increasingly precise voltage control is being required in analog integrated circuits, creating a strong need to stabilize the characteristics of resistance elements by reducing variations in resistance value between resistance elements in the same circuit. When the resistance elements are formed as taught by Iwai, their electrical characteristics are affected by variations in the substrate potential and, because of the thinness of the oxide film 121 and consequent proximity of the diffusion regions 103 to the polysilicon layer 107, by variations in the power supply voltage applied to the polysilicon layer 107.